From: Alex Williamson <alex.williamson@hp.com>
Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
-#ifndef CONFIG_DM
#ifdef __powerpc__
static inline int testandset (int *p)
{
return __sync_lock_test_and_set (p, 1);
}
#endif
-#endif /* !CONFIG_DM */
typedef int spinlock_t;
}
#ifdef __ia64__
+
+#define __ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
+#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
+#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
+
/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
* So to emulate right behavior that guest OS is assumed, we need to flush
* I/D cache here.